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| HY57V56820B(L)T 4 Banks x 8M x 8Bit Synchronous DRAM DESCRIPTION The HY57V56820B is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. The HY57V56820B is organized as 4banks of 8,388,608x8. The HY57V56820B is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL. Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not restricted by a 2N rule.) FEATURES * * * Single 3.30.3V power supply All device pins are compatible with LVTTL interface JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin pitch All inputs and outputs referenced to positive edge of system clock Data mask function by DQM Internal four banks operation * * * * Auto refresh and self refresh 8192 refresh cycles / 64ms Programmable Burst Length and Burst Type - 1, 2, 4, 8 or Full page for Sequential Burst * - 1, 2, 4 or 8 for Interleave Burst Programmable CAS Latency ; 2, 3 Clocks * * ORDERING INFORMATION Part No. HY57V56820BT-6 HY57V56820BT-K HY57V56820BT-H HY57V56820BT-8 HY57V56820BT-P HY57V56820BT-S HY57V56820BLT-6 HY57V56820BLT-K HY57V56820BLT-H HY57V56820BLT-8 HY57V56820BLT-P HY57V56820BLT-S Clock Frequency 166MHz 133MHz 133MHz 125MHz 100MHz 100MHz 166MHz 133MHz 133MHz 125MHz 100MHz 100MHz Power Organization Interface Package Normal 4Banks x 8Mbits x8 LVTTL 400mil 54pin TSOP II Low power This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.4/Mar. 02 1 HY57V56820B(L)T PIN CONFIGURATION VDD DQ0 VDDQ NC DQ1 VSSQ NC DQ2 VDDQ NC DQ3 VSSQ NC VDD NC /WE /CAS /RAS /CS BA0 BA1 A10/AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 54pin TSOP II 42 400mil x 875mil 41 0.8mm pin pitch 40 39 38 37 36 35 34 33 32 31 30 29 28 VSS DQ7 VSSQ NC DQ6 VDDQ NC DQ5 VSSQ NC DQ4 VDDQ NC VSS NC DQM CLK CKE A12 A11 A9 A8 A7 A6 A5 A4 VSS PIN DESCRIPTION PIN CLK CKE CS BA0, BA1 A0 ~ A12 Clock Clock Enable Chip Select Bank Address Address Row Address Strobe, Column Address Strobe, Write Enable Data Input/Output Mask Data Input/Output Power Supply/Ground Data Output Power/Ground No Connection PIN NAME DESCRIPTION The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh Enables or disables all inputs except CLK, CKE and DQM Selects bank to be activated during RAS activity Selects bank to be read/written during CAS activity Row Address : RA0 ~ RA12, Column Address : CA0 ~ CA9 Auto-precharge flag : A10 RAS, CAS and WE define the operation Refer function truth table for details Controls output buffers in read mode and masks input data in write mode Multiplexed data input / output pin Power supply for internal circuits and input buffers Power supply for output buffers No connection RAS, CAS, WE DQM DQ0 ~ DQ7 VDD/VSS VDDQ/VSSQ NC Rev. 1.4/Mar. 02 2 HY57V56820B(L)T FUNCTIONAL BLOCK DIAGRAM 8Mbit x 4banks x 8 I/O Synchronous DRAM Self refresh logic & timer Internal Row counter CLK Row active 8Mx8 Bank3 Row Pre Decoders 8Mx8 Bank2 X decoders 8Mx8 Bank1 X decoders 8Mx8 Bank0 X decoders DQ0 DQ1 I/O Buffer & Logic Sense AMP & I/O Gate CKE CS State Machine RAS CAS WE DQM X decoders refresh Column Active Memory Cell Array Column Pre Decoders DQ6 DQ7 Y decoders Bank Select Column Add Counter A0 A1 Address buffers A12 BA0 BA1 Address Registers Burst Counter Mode Registers CAS Latency Data Out Control Pipe Line Control Rev. 1.4/Mar. 02 3 HY57V56820B(L)T ABSOLUTE MAXIMUM RATINGS Parameter Ambient Temperature Storage Temperature Voltage on Any Pin relative to VSS Voltage on VDD relative to VSS Short Circuit Output Current Power Dissipation Soldering Temperature Time TA TSTG VIN, VOUT VDD, VDDQ IOS PD TSOLDER Symbol 0 ~ 70 -55 ~ 125 -1.0 ~ 4.6 -1.0 ~ 4.6 50 1 260 10 Rating C C V V mA W C Sec Unit Note : Operation at above absolute maximum rating can adversely affect device reliability DC OPERATING CONDITION (TA=0 to 70C) Parameter Power Supply Voltage Input High Voltage Input Low Voltage Symbol VDD, VDDQ VIH VIL Min 3.0 2.0 - 0.3 Typ. 3.3 3.0 0 Max 3.6 VDD + 0.3 0.8 Unit V V V Note 1 1,2 1,3 Note : 1.All voltages are referenced to VSS = 0V 2.VIH (max) is acceptable 5.6V AC pulse width with 3ns of duration 3.VIL (min) is acceptable -2.0V AC pulse width with 3ns of duration AC OPERATING CONDITION (TA=0 to 70C, VDD=3.3 0.3V, VSS=0V) Parameter AC Input High / Low Level Voltage Input Timing Measurement Reference Level Voltage Input Rise / Fall Time Output Timing Measurement Reference Level Output Load Capacitance for Access Time Measurement Symbol VIH / VIL Vtrip tR / tF Voutref CL Value 2.4/0.4 1.4 1 1.4 50 Unit V V ns V pF 1 Note Note : 1. Output load to measure access time is equivalent to two TTL gates and one capacitor (50pF) For details, refer to AC/DC output circuit Rev. 1.4/Mar. 02 4 HY57V56820B(L)T CAPACITANCE (TA=25C, f=1MHz) -6/K/H Parameter Input capacitance CLK A0 ~ A12, BA0, BA1, CKE, CS, RAS, CAS, WE, UDQM, LDQM Data input / output capacitance DQ0 ~ DQ15 Pin Symbol Min CI1 CI2 CI/O 2.5 2.5 4.0 Max 3.5 3.8 6.5 Min 2.5 2.5 4.0 Max 4.0 5.0 6.5 pF pF pF -8/P/S Unit OUTPUT LOAD CIRCUIT Vtt=1.4V RT=250 Output Output 50pF 50pF DC Output Load Circuit AC Output Load Circuit DC CHARACTERISTICS I (TA=0 to 70C, VDD=3.30.3V) Parameter Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage ILI ILO VOH VOL Symbol Min. -1 -1 2.4 Max 1 1 0.4 Unit uA uA V V Note 1 2 IOH = -4mA IOL = +4mA Note : 1.VIN = 0 to 3.6V, All other pins are not tested under VIN =0V 2.DOUT is disabled, VOUT=0 to 3.6V Rev. 1.4/Mar. 02 5 HY57V56820B(L)T DC CHARACTERISTICS II (TA=0 to 70C, VDD=3.30.3V, VSS=0V) Speed Parameter Symbol Test Condition -6 Operating Current Precharge Standby Current in Power Down Mode IDD1 IDD2P IDD2PS IDD2N Precharge Standby Current in Non Power Down Mode IDD2NS Active Standby Current in Power Down Mode IDD3P IDD3PS IDD3N Active Standby Current in Non Power Down Mode IDD3NS Burst Mode Operating Current Auto Refresh Current Self Refresh Current Burst length=1, One bank active tRC tRC(min), IOL=0mA CKE VIL(max), tCK = 15ns CKE VIL(max), tCK = CKE VIH(min), CS VIH(min), tCK = 15ns Input signals are changed one time during 30ns. All other pins VDD-0.2V or 0.2V CKE VIH(min), tCK = Input signals are stable. CKE VIL(max), tCK = 15ns CKE VIL(max), tCK = CKE VIH(min), CS VIH(min), tCK = 15ns Input signals are changed one time during 30ns. All other pins VDD-0.2V or 0.2V CKE VIH(min), tCK = Input signals are stable. tCK tCK(min), IOL=0mA All banks active CL=3 CL=2 150 140 240 130 140 220 130 Unit -K 120 Note -H 120 2 -8 120 -P 110 -S 110 mA 1 mA 1 30 mA 15 5 mA 5 40 mA 30 130 140 220 3 1.5 130 140 200 110 120 200 110 mA 120 200 mA mA mA 2 3 4 1 IDD4 IDD5 IDD6 tRRC tRRC(min), All banks active CKE 0.2V Note : 1.IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open 2.Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II 3.HY57V56820BT-6/H/8/P/S 4.HY57V56820BLT-6/H/8/P/S Rev. 1.4/Mar. 02 6 HY57V56820B(L)T AC CHARACTERISTICS I (AC operating conditions unless otherwise noted) -6 Parameter Symbol Min System Clock Cycle Time CAS Latency = 3 CAS Latency = 2 tCK3 tCK2 tCHW tCLW tAC3 tAC2 tOH tDS tDH tAS tAH tCKS tCKH tCS tCH tOLZ tOHZ3 tOHZ2 6 1000 10 2.5 2.5 2.7 1.5 0.8 1.5 0.8 1.5 0.8 1.5 0.8 1 2.7 2.7 5.4 6 5.4 5.4 7.5 2.5 2.5 2.7 1.5 0.8 1.5 0.8 1.5 0.8 1.5 0.8 1 2.7 2.7 5.4 5.4 5.4 5.4 Max Min 7.5 1000 10 2.5 2.5 2.7 1.5 0.8 1.5 0.8 1.5 0.8 1.5 0.8 1 2.7 3 5.4 6 5.4 6 Max Min 7.5 1000 10 3 3 3 2 1 2 1 2 1 2 1 1 3 3 6 6 6 6 Max Min 8 1000 10 3 3 3 2 1 2 1 2 1 2 1 1 3 3 6 6 6 6 Max Min 10 1000 12 3 3 3 2 1 2 1 2 1 2 1 1 3 3 6 6 6 6 Max Min 10 1000 ns ns ns ns 2 CAS Latency = 2 ns ns ns ns ns ns ns ns ns ns ns ns ns 1 1 1 1 1 1 1 1 1 1 Max ns -K -H -8 -P -S Unit Note Clock High Pulse Width Clock Low Pulse Width Access Time From Clock CAS Latency = 3 Data-Out Hold Time Data-Input Setup Time Data-Input Hold Time Address Setup Time Address Hold Time CKE Setup Time CKE Hold Time Command Setup Time Command Hold Time CLK to Data Output in Low-Z Time CLK to Data Output in High-Z Time CAS Latency = 3 CAS Latency = 2 Note : 1.Assume tR / tF (input rise and fall time ) is 1ns 2.Access times to be measured with input signals of 1v/ns edge rate Rev. 1.4/Mar. 02 7 HY57V56820B(L)T AC CHARACTERISTICS II -6 Parameter Symbol Min Operation RAS Cycle Time Auto Refresh RAS to CAS Delay RAS Active Time RAS Precharge Time RAS to RAS Bank Active Delay CAS to CAS Delay Write Command to Data-In Delay Data-In to Precharge Command Data-In to Active Command DQM to Data-Out Hi-Z DQM to Data-In Mask MRS to New Command Precharge to Data Output Hi-Z CAS Latency = 3 CAS Latency = 2 tRRC tRCD tRAS tRP tRRD tCCD tWTL tDPL tDAL tDQZ tDQM tMRD tPROZ3 tPROZ2 tPDE tSRE tREF 60 18 42 18 12 1 0 2 5 2 0 2 3 2 1 1 100K 64 60 15 45 15 15 1 0 2 5 2 0 2 3 2 1 1 100K 64 65 20 45 20 15 1 0 2 5 2 0 2 3 2 1 1 100K 64 68 20 48 20 16 1 0 2 5 2 0 2 3 2 1 1 100K 64 70 20 50 20 20 1 0 2 5 2 0 2 3 2 1 1 100K 64 70 20 50 20 20 1 0 2 5 2 0 2 3 2 1 1 100K 64 ns ns ns ns ns CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK ms 1 tRC 60 Max Min 60 Max Min 65 Max Min 68 Max Min 70 Max Min 70 Max ns -K -H -8 -P -S Unit Note Power Down Exit Time Self Refresh Exit Time Refresh Time Note : 1. A new command can be given tRRC after self refresh exit Rev. 1.4/Mar. 02 8 HY57V56820B(L)T IBIS SPECIFICATION IOH Characteristics (Pull-up) Voltage (V) 3.45 3.3 3.0 2.6 2.4 2.0 1.8 1.65 1.5 1.4 1.0 0 0 -21.1 -34.1 -58.7 -67.3 -73 -77.9 -80.8 -88.6 -93 100MHz (Min) I(mA) 100MHz (Max) I(mA) -2.4 -27.3 -74.1 -129.2 -153.3 -197 -226.2 -248 -269.7 -284.3 -344.5 -502.4 -0.7 -7.5 -13.3 -27.5 -35.5 -41.1 -47.9 -52.4 -72.5 -93 66MHz (Min) I(mA) 66MHz and 100MHz Pull-up 0 0 -100 -200 I (mA) -300 -400 -500 -600 Voltage (V) IOH Min (100MHz) IOH Min (66MHz) IOH Max (66 /100MHz) 0.5 1 1.5 2 2.5 3 3.5 IOL Characteristics (Pull-down) Voltage (V) 0 0.4 0.65 0.85 1.0 1.4 1.5 1.65 1.8 1.95 3.0 3.45 100MHz (Min) I(mA) 0 27.5 41.8 51.6 58.0 70.7 72.9 75.4 77.0 77.6 80.3 81.4 100MHz (Max) I(mA) 0 70.2 107.5 133.8 151.2 187.7 194.4 202.5 208.6 212.0 219.6 222.6 66MHz (Min) I(mA) 0 17.7 66MHz and 100MHz Pull-down 250 200 150 100 50 0 0 0.5 1 1.5 2 2.5 3 3.5 Voltage (V) IOL Min (100MHz) IOL Min (66MHz) IOL Max (100MHz) 33.3 37.6 46.6 48.0 49.5 50.7 51.5 54.2 54.9 Rev. 1.4/Mar. 02 I (mA) 26.9 9 HY57V56820B(L)T DEVICE OPERATING OPTION TABLE HY57V56820B(L)T-6 CAS Latency 166MHz(6ns) 143MHz(7ns) 133MHz(7.5ns) 3CLKs 3CLKs 2CLKs tRCD 3CLKs 3CLKs 3CLKs tRAS 7CLKs 6CLKs 6CLKs tRC 10CLKs 9CLKs 9CLKs tRP 3CLKs 3CLKs 3CLKs tAC 5.4ns 5.4ns 5.4ns tOH 2.7ns 2.7ns 2.7ns HY57V56820B(L)T-K CAS Latency 133MHz(7.5ns) 125MHz(8ns) 100MHz(10ns) 2CLKs 3CLKs 2CLKs tRCD 2CLKs 3CLKs 2CLKs tRAS 6CLKs 6CLKs 6CLKs tRC 8CLKs 9CLKs 9CLKs tRP 2CLKs 3CLKs 3CLKs tAC 5.4ns 6ns 6ns tOH 2.7ns 3ns 3ns HY57V56820B(L)T-H CAS Latency 133MHz(7.5ns) 125MHz(8ns) 100MHz(10ns) 3CLKs 3CLKs 2CLKs tRCD 3CLKs 3CLKs 2CLKs tRAS 7CLKs 6CLKs 5CLKs tRC 10CLKs 9CLKs 7CLKs tRP 3CLKs 3CLKs 2CLKs tAC 5.4ns 6ns 6ns tOH 2.7ns 3ns 3ns HY57V56820B(L)T-8 CAS Latency 125MHz(8ns) 100MHz(10ns) 83MHz(12ns) 3CLKs 2CLKs 2CLKs tRCD 3CLKs 2CLKs 2CLKs tRAS 6CLKs 5CLKs 4CLKs tRC 9CLKs 7CLKs 6CLKs tRP 3CLKs 2CLKs 2CLKs tAC 6ns 6ns 6ns tOH 3ns 3ns 3ns HY57V56820B(L)T-P CAS Latency 100MHz(10ns) 83MHz(12ns) 66MHz(15ns) 2CLKs 2CLKs 2CLKs tRCD 2CLKs 2CLKs 2CLKs tRAS 5CLKs 5CLKs 4CLKs tRC 7CLKs 7CLKs 6CLKs tRP 2CLKs 2CLKs 2CLKs tAC 6ns 6ns 6ns tOH 3ns 3ns 3ns HY57V56820B(L)T-S CAS Latency 100MHz(10ns) 83MHz(12ns) 66MHz(15ns) 3CLKs 2CLKs 2CLKs tRCD 2CLKs 2CLKs 2CLKs tRAS 5CLKs 5CLKs 4CLKs tRC 7CLKs 7CLKs 6CLKs tRP 2CLKs 2CLKs 2CLKs tAC 6ns 6ns 6ns tOH 3ns 3ns 3ns Rev. 1.4/Mar. 02 10 HY57V56820B(L)T COMMAND TRUTH TABLE Command Mode Register Set No Operation Bank Active Read H Read with Autoprecharge Write H Write with Autoprecharge Precharge All Banks H Precharge selected Bank Burst Stop DQM Auto Refresh Burst-Read-SingleWRITE Entry Self Refresh1 Exit H H H H H L H X L H L H Entry Precharge power down Exit L H L H Clock Suspend Entry Exit H L L L H V X V V X H X H X H X X X H L L H H X H X H X X X H X H X H X X L L L H X L H X L L L X L L L X H H H X X H L X V X X X X X L L H L X X L X X X A9 Pin High (Other Pins OP code) V X L H L L X CA H H X X L H L H X CA H L V CKEn-1 H H H CKEn X X L X L H L H H H H X RA L V V CS L H RAS L X CAS L X WE L X X X DQM X ADDR A10/ AP OP code BA Note Note : 1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high 2. X = Dont care, H = Logic High, L = Logic Low. BA =Bank Address, RA = Row Address, CA = Column Address, Opcode = Operand Code, NOP = No Operation Rev. 1.4/Mar. 02 11 HY57V56820B(L)T PACKAGE INFORMATION 400mil 54pin Thin Small Outline Package UNIT : mm(inch) 11.938(0.4700) 11.735(0.4620) 22.327(0.8790) 22.149(0.8720) 0.150(0.0059) 0.050(0.0020) 10.262(0.4040) 10.058(0.3960) 1.194(0.0470) 0.991(0.0390) 0.80(0.0315)BSC 0.400(0.016) 0.300(0.012) 5deg 0deg 0.597(0.0235) 0.406(0.0160) 0.210(0.0083) 0.120(0.0047) Rev. 1.4/Mar. 02 12 |
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